1. Field of the Invention
This invention relates to devices, methods, and systems for conducting analog-to-digital conversions. Specifically, the invention relates to devices, methods, and systems for conducting analog-to-digital conversions using analog comparators.
2. Description of the Related Art
A flash or parallel analog-to-digital (A/D) converter is useful for high-speed applications due to its single clock cycle conversion capability. Typical applications include data acquisition, video capture, video compression, and the like.
The architecture for a classical flash A/D converter is described in a variety of tutorial sources, including D. A. Johns and K. Martin, Analog Integrated Circuit Design,John Wiley and sons, New York, 1997, chapter 13. As depicted in FIG. 1, a classic A/D architecture 100 for a parallel A/D converter employs a resistor string 110, a comparator bank 120, a digital encoder 125, and an output register 150. In the depicted architecture, the digital encoder 125 comprises a one-high encoder 130 and a binary encoder 140. As depicted, conversion of an analog input signal (not shown) begins on the rising edge of a conversion clock 102. A delayed version of the conversion clock 102 is provided by the delay element 170 as the delayed conversion clock 172. In the depicted embodiment, the delayed conversion clock 172 is used to latch the digital code 142 into the output register 150 and complete the analog-to-digital conversion cycle. While the depicted architecture illustrates a digital encoder 125 that provides binary codes, the digital encoder 125 may be configured to provide other codes such as Grey codes.
The schematic diagram of FIG. 2 illustrates in greater detail a 3-bit example of the classical A/D architecture 100. The depicted example requires seven single-bit comparators 220 within the comparator bank 120 to produce three digital output bits within the digital code 142. The digital encoder 125 translates the output signals from the seven single bit comparators 220 to the three-bit digital code 142. In general, classical flash architectures require 2N−1 comparators and associated logic gates to produce an output of N digital bits. Thus, the complexity, cost, and power consumption of a flash converter is typically proportional to 2N−1.
The reference inputs for the comparators 220 are preferably biased by a monotonically increasing series of reference voltages 112. For example, the reference voltages may be provided by a set of resistors arranged in series within the resistor string 110 such that the reference voltages 112 range from a near zero value at the first comparator to a maximum value at the last comparator.
Each of the comparators 220 compares an input signal, such as the input signal 202, with one of the reference voltages 112. In the depicted embodiment, the comparators begin each conversion cycle with their output at a low voltage corresponding to a binary zero state. Conversion commences with the rising edge of the conversion clock 102. Those comparators that are provided with reference voltages lower than the input signal 202 drive their corresponding output to a high voltage, while the remaining comparators maintain their outputs at a low voltage.
In the depicted configuration, the outputs of the comparators 220 provide what is sometimes referred to as a “thermometer” code in that all outputs above a transition point have a low value, while those outputs below the transition point have a high value. The provided thermometer code is typically applied to a set of logic gates such as those shown within the one-high encoder 130 of FIG. 2. The logic gates convert the thermometer code to a “one high” code in which the high valued bit corresponds to the transition point. The “one high” digital code is then applied to additional logic such as the depicted binary encoder 140 to produce the digital code 142.
Due to the exponential increase in complexity associated with additional resolution, commercial flash A/D converters are typically limited to 8 or fewer bits of resolution. For example, an 8-bit flash A/D converter would require 255 comparators. Increasing the resolution to 10-bits would require 1023 comparators or a four-fold increase over an 8-bit converter.
In addition to an exponential increase in the number of comparators, additional resolution typically requires higher precision components to match the increased resolution. For example, the transistors that comprise the comparators may require tighter width-to-length ratio tolerances to achieve the desired precision. Tighter tolerances on transistor dimensions are typically accomplished by increasing the overall size of the transistors. Increasing the transistor sizes further increases the exponential growth in both circuit area and power consumption.
Due to the challenges and barriers to increasing conversion resolution, A/D converter designers have sought solutions to the problem and have devised some possible solutions. The idea of “interpolation,” as discussed in chapter 13 of Johns and Martin, Analog Integrated Circuit Design, is one such solution. As discussed therein, prior art interpolating converters interpolate the output of the amplifier stages of adjacent comparators, using for example a voltage divider circuit to provide additional inputs into the latching stages.
Voltage or current interpolation potentially simplifies comparator circuitry used within a typical flash converter. Although practical, voltage or current interpolation has several disadvantages. For example, currently available interpolation techniques typically require amplifiers that exhibit a linear response for small input signals. Requiring a linear response further constrains the comparator circuit, often resulting in less than optimal speed. Another disadvantage of currently available interpolation techniques is the need for linear summing of the amplifier stage output signals. Linear summing is normally accomplished by resistors or capacitors, which adds complexity and presents precision matching challenges.
Another method for reducing the number of comparators required for additional resolution is to use a “folding” technique. A folding technique facilitates using the same comparator for multiple levels of signal input. The folding technique is discussed in Johns and Martin as well as in U.S. Pat. No. 6,169,510. Comparator reuse requires the addition of very precise folding circuits to process the input signal and in some cases may result in a reduction of A/D converter accuracy due to either static or dynamic errors introduced by the folding circuits. Other less general methods have been proposed such as using a second “ranging” comparator and digital select logic. This approach requires additional complexity and additional time for a conversion to take place. Yet another widely used approach to reducing the number of comparators is the two-stage flash (flash-flash) architecture, which generates N digital bits in two separate clock cycles. A variation of the classical flash-flash architecture is the subranging architecture, which also requires two clock cycles for a complete conversion. Two stage and subranging A/D converter architectures are described in chapter 13 of Johns and Martin.
What is needed is an apparatus and method to increase the resolution of A/D conversions without an exponential increase in circuit complexity and other limitations imposed by current techniques. Such an increased resolution needs to be implemented in a manner that does not interfere with a flash converter's ability to convert within a single clock cycle.